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After marking an FPGA IP VI as top-level and placing the controls and indicators of the FPGA IP VI on the connector pane, you can call the FPGA IP VI from other document types.

FPGA IP VI in a Top-Level VI

To call an FPGA IP VI from a top-level VI, you must place the FPGA IP VI within a Clock-Driven Loop and wire the handshaking inputs to the node and the clock input to the loop, as shown in the following image.

FPGA IP VI in a VI Diagram

To call an FPGA IP VI from a VI Diagram, you need only place the FPGA IP VI on the diagram.

FPGA IP VI in a Multirate Diagram

To call an FPGA IP VI from a Multirate Diagram, you need only place the FPGA IP VI on the diagram.