The process of transferring your FPGA IP VI to hardware includes setting performance directives for your FPGA IP VI, estimating the FPGA resources it requires, and optimizing your design if it does not meet performance requirements. The following flowchart outlines the process. Click the blue rectangles for more information about each step.
If your compilation does not succeed, investigate build errors for failed items in the Compile Queue pane. Investigating build errors opens the Timing Violations pane, which you can use to determine what part of the design failed to meet timing requirements. If timing failed in the FPGA IP VI, adjust the performance directives for the VI. If timing fails elsewhere in the application, debug that part of the application.