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When building a complete application, you create top-level VIs, Clock-Driven Logic, and Multirate Diagram documents in addition to FPGA IP VIs. Before you can call an FPGA IP VI from the other document types, you must mark the FPGA IP VI as top-level and place controls and indicators on its connector pane.

You can mark only one VI as top-level within an FPGA IP container. If you want to call more than one FPGA IP VI from another document, you can either place subVIs in the top-level VI or store your top-level VIs in more than one FPGA IP container.

  1. Open SystemDesigner.
  2. Within the FPGA IP container in SystemDesigner, click the VI you want to mark as top-level.
  3. On the Configure tab, in the Organize group, enable Mark as Top-Level.
  4. Open the VI.
  5. Select a control or indicator from either the diagram or panel.
  6. On the Configure tab, in the Usage group, enable On Connector Pane.
  7. Repeat steps 5 through 6 for any other controls or indicators in your VI.