You must initialize all array shift registers in FPGA IP VIs. Initializing an array shift register allows the compiler to determine initial values for the shift register and make optimizations, which helps increase throughput by preventing re-initialization on consecutive executions of the FPGA IP VI.
In complex designs, the compiler still might not be able to determine whether the initial array values are important and may not make the automatic optimizations it normally would when you initialize array shift registers. If your FPGA IP VI does not achieve the desired throughput, you can manually initialize the array shift register using a Feedback Node design to mimic the optimization the compiler would have made.
The following code demonstrates an example of original code and an equivalent representation after the compiler optimizes the code based on initialization values for the shift register.
When the original code is compiled, the compiler determines that the loop overwrites every element of the array. Because of this determination, the compiler makes optimizations to the FPGA IP code where the value of the left shift register isn't initialized on each execution of the VI, as demonstrated in the following image.
The previous image is also an example of how you might modify your code to mimic the optimization the compiler would have made in a complex design where the compiler can't automatically make optimizations.