If you estimate an FPGA IP VI and find that the design does not meet your performance requirements, or if an FPGA IP VI does not compile successfully, adjust the routing margin, resource budget, and clock rate to improve the results.
A higher routing margin improves performance results by allowing more time for routing delays between the logic elements on the FPGA. Allowing more time for routing delays tends to increase the number of pipeline stages in the design, which in turn results in a higher achievable clock rate.
If the FPGA IP VI utilizes too many FPGA resources, you can decrease the resource budget to make those resources available for other parts of the application. If the FPGA IP VI was previously constrained, you can increase the resource budget to achieve a higher throughput rate for the design.