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If you estimate an FPGA IP VI and find that the design does not meet your performance requirements, or if an FPGA IP VI does not compile successfully, adjust the routing margin, resource budget, and clock rate to improve the results.

  1. Access the routing margin, resource budget, and clock rate settings using either of the following methods:
    • Select an FPGA IP node from a top-level FPGA VI. On the Configure tab, click Advanced, and use the estimation options in the Advanced Estimation Settings dialog box.
    • Open an FPGA IP VI. On the VI tab, click FPGA Estimates to open the VI Estimation dialog box. Use the estimation options on the Advanced tab.
  2. Raise the routing margin of the FPGA IP VI.

    A higher routing margin improves performance results by allowing more time for routing delays between the logic elements on the FPGA. Allowing more time for routing delays tends to increase the number of pipeline stages in the design, which in turn results in a higher achievable clock rate.

  3. Adjust the resource budget of the FPGA IP VI.

    If the FPGA IP VI utilizes too many FPGA resources, you can decrease the resource budget to make those resources available for other parts of the application. If the FPGA IP VI was previously constrained, you can increase the resource budget to achieve a higher throughput rate for the design.

  4. Estimate the FPGA IP VI.
  5. (Optional) If adjusting the routing margin and resource budget fails to improve the results, increase or decrease the clock rate. A design that fails to compile due to timing violations may compile successfully at a different clock rate.