To specify VIs as FPGA IP documents, you place them inside an FPGA IP container in SystemDesigner. Complete the following steps to add FPGA IP containers and VIs to SystemDesigner:
In SystemDesigner, add an FPGA IP container within Source Code on the controller or FPGA target.
You can add FPGA IP containers on controllers and FPGA targets. The recommended workflow is to create the FPGA IP algorithm on the controller, test it, then transfer it to the FPGA target.
Double-click the FPGA IP container you created.
Add a VI to the FPGA IP container.
You can add multiple VIs to the same FPGA IP container. However, you can select only one top-level VI. The top-level VI is the VI you can call from other parts of your application, such as a Multirate Diagram.
LabVIEW creates the new VI within the FPGA IP container, which marks the VI as an FPGA IP document.