Transferring Data between a Target and Host Using FIFOs

Before completing this task, verify that FIFOs are the best data storage and transfer option for your application.

Use FIFOs to transfer data between an FPGA target and a host processor without data loss.

What to Use

• Open FPGA VI Reference
• Run FPGA VI
• Write DMA FIFO
• Read DMA FIFO
• Close FPGA VI
• Read FIFO (Clock-Driven Logic)
• Write FIFO (Clock-Driven Logic)

What to Do

1. Create the following diagram in a G VI targeted to your host processor.

   Customize the gray sections for your unique programming goals.

   

   	Use the RIO address for your FPGA found in Measurement & Automation Explorer (MAX) to specify an FPGA target. To ensure your code runs on the FPGA, the RIO address input must match the FPGA target RIO Alias.
   	Select Open FPGA VI Reference and assign a bitfile or build specification on the Configure tab. You must assign a bitfile or build specification before you can select FIFO references for Write DMA FIFO and Read DMA FIFO. Note   If no build specification appears on the Configure tab, create a top-level VI on the FPGA target in SystemDesigner before you configure Open FPGA VI Reference. LabVIEW automatically creates a build specification for each top-level VI on the FPGA target in SystemDesigner.
   	Perform operations using the host processor before transferring data to the FPGA target. The data you write to Write DMA FIFO must use the same data type that you need in your FPGA VI. Convert data types from the host processor to the data type of the FIFO you specify for Write DMA FIFO.
   	Create a Host to Target FIFO in SystemDesigner. Select Write DMA FIFO and specify the reference to the Host to Target FIFO on the Configure tab.
   	Create a Target to Host FIFO in SystemDesigner. Select Read DMA FIFO and specify the reference to the Target to Host FIFO on the Configure tab.
   	The data output from Read DMA FIFO contains data written to the DMA FIFO from the FPGA target. Use this output to display data from the FPGA target on the host, or use the host to further process the output data using the host processor.

2. Create the following diagram in a G VI diagram targeted to your FPGA.

   Customize the gray sections for your unique programming goals.

   

	Use a FIFO constant to reference the Host to Target FIFO you created in SystemDesigner. Use the same FIFO reference for Read FIFO that you specify for Write DMA FIFO on the host VI.
	Process the data sent from the host. Use handshaking when working with nodes that have a latency of greater than one clock cycle to ensure the FPGA writes valid data.
	Use a FIFO constant to reference the Target to Host FIFO you created in SystemDesigner. Use the same FIFO reference for Write FIFO that you specify for Read DMA FIFO on the host VI.

Troubleshooting

• If you receive unexpected or invalid data on your host from your target:
  • Check that the RIO address for your hardware is correct. Verify the RIO address input you use in LabVIEW matches the RIO Alias listed for your hardware device in NI Measurement & Automation Explorer (MAX).
  • Check that the FIFO references on the host match the FIFO references on the target. The FIFO you configure for Write DMA FIFO on the host must match the FIFO reference you send to Read FIFO on the FPGA target. The FIFO you configure for Read DMA FIFO on the host must match the FIFO reference you send to Write FIFO on the FPGA target.
• If no build specification appears on the Configure tab when you select Open FPGA VI, create a top-level VI on the FPGA target in SystemDesigner before you configure Open FPGA VI Reference. LabVIEW automatically creates a build specification for each top-level VI on the FPGA target in SystemDesigner.

Examples

Search LabVIEW for the following installed examples:

• FIFO
• FPGA Host Interface
• FPGA IP Interfaces