Before completing this task, verify that FIFOs are the best data storage and transfer option for your application.
Use FIFOs to transfer data between an FPGA target and a host processor without data loss.
What to Use
What to Do
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Create the following diagram in a G VI targeted to your host processor.
Customize the gray sections for your unique programming goals.
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Create the following diagram in a G VI diagram targeted to your FPGA.
Customize the gray sections for your unique programming goals.
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Use a FIFO constant to reference the Host to Target FIFO you created in SystemDesigner. Use the same FIFO reference for Read FIFO that you specify for Write DMA FIFO on the host VI. |
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Process the data sent from the host. Use handshaking when working with nodes that have a latency of greater than one clock cycle to ensure the FPGA writes valid data. |
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Use a FIFO constant to reference the Target to Host FIFO you created in SystemDesigner. Use the same FIFO reference for Write FIFO that you specify for Read DMA FIFO on the host VI. |
Troubleshooting
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If you receive unexpected or invalid data on your host from your target:
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Check that the RIO address for your hardware is correct. Verify the RIO address input you use in LabVIEW matches the RIO Alias listed for your hardware device in NI Measurement & Automation Explorer (MAX).
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Check that the FIFO references on the host match the FIFO references on the target. The FIFO you configure for Write DMA FIFO on the host must match the FIFO reference you send to Read FIFO on the FPGA target. The FIFO you configure for Read DMA FIFO on the host must match the FIFO reference you send to Write FIFO on the FPGA target.
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If no build specification appears on the Configure tab when you select Open FPGA VI, create a top-level VI on the FPGA target in SystemDesigner before you configure Open FPGA VI Reference. LabVIEW automatically creates a build specification for each top-level VI on the FPGA target in SystemDesigner.
Examples
Search LabVIEW for the following installed examples:
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FIFO
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FPGA Host Interface
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FPGA IP Interfaces