Testing an application, and the pieces of the application, allows you to ensure that the application functions as you expect and helps to prevent errors later in development.
Test your application on three levels: unit, component, and system. Testing smaller portions of code as you create them saves time by identifying and preventing errors and bugs as your program grows. If you test and debug the functionality of the code extensively at the unit and component levels, you reduce the potential for errors at the system level.
Refer to the following guidelines for help identifying units, components, and systems:
Create testbenches to test individual units and components of your application as you complete them. A testbench is typically a VI that provides simulated input values to your code and displays the output of the code on the panel. When your system is complete, you can create a testbench that runs your entire application, or you can simply run your host application.
The following list provides examples of tests you might perform on various FPGA-targeted documents:
Multirate Diagram on the host—
When developing a Multirate Diagram on the host, call the Multirate Diagram from a testbench VI on the host. Unit test Multirate Diagrams on the host before you convert the floating-point data types in the document to fixed-point so you can more easily adjust your design based on the test results.
Multirate Diagram in an FPGA VI—To test a Multirate Diagram called by an FPGA VI, create a testbench VI on the FPGA that uses FIFO references to send data samples to the Multirate Diagram.
FPGA IP on the host—When developing an FPGA IP VI on the host, call the FPGA IP VI from a testbench VI on the host. Unit test FPGA IP VIs on the host before you convert the floating-point data types in the document to fixed-point so you can more easily adjust your design based on the test results.
FPGA IP in Clock-Driven Logic—To test an FPGA IP VI called by Clock-Driven Logic (CDL), make sure the FPGA IP VI is in a CDL document, and then use a Run FPGA Simulation node to call the CDL document from a testbench VI on the host.
Clock-Driven Logic—To test CDL code, use a Run FPGA Simulation node to call the CDL document from a testbench VI on the host.
Mixed languages in an FPGA VI—To test code that mixes languages in an FPGA VI, such as a single Clock-Driven Loop that calls FPGA IP and communicates with a Multirate Diagram, place the code in a top-level FPGA VI testbench. Use FPGA Host Interface nodes in a host VI to run the FPGA testbench in simulation on the host.
Top-Level FPGA VI—To test your entire application, also known as the system, use FPGA Host Interface nodes in a host VI to run the top-level FPGA VI in simulation on the host.