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Sends a register write instruction to the FPGA.

Input Parameters
  • session in—Identifies your session. Obtain session in from Register Bus Open Session.
  • register write—Specifies the subsystem ID, address, and data for the register write operation.
  • register write.subsystem—Specifies the destination subsystem for the register read or write operation.
  • register write.address—Specifies the destination address in the register write.subsystem parameter.
  • register write.data—Specifies the data to be written to the register.
  • timeout (1000 ms)—Specifies the minimum time, in ms, for Write Register to wait before timing out. The Write Register times out if the host part of the Host to Target DMA FIFO used by this Register Bus session does not contain enough space to write instructions for the register write before the timeout (1000 ms) that you specify elapses. Write Register also times out if the wait until committed parameter is set to TRUE, and a notification from the FPGA VI indicating that the register write has been processed does not arrive before the timeout (1000 ms) that you specify elapses. Set this parameter to -1 if you want Write Register to wait indefinitely. The default value is 1,000 ms.
  • error in—Describes error conditions that occur before this node runs. This input provides standard error in functionality.
  • wait until committed—Indicates whether this node should block execution until it receives a notification from the FPGA VI indicating that the FPGA VI has received and processed the register write data. This is an optional parameter. If you set wait until committed to FALSE, the register write instruction is written into the instruction FIFO, but they may be processed by the FPGA VI after this node has finished executing. The default value is TRUE.

Output Parameters

  • session out—Passes a reference to your session to the next node.
  • error out—Contains error information. This output provides standard error out functionality.

Installed By: LabVIEW Communications System Design Suite (introduced in 1.0)

Where This Node Can Run:

Desktop OS: Windows

FPGA: Not supported