Synchronously realizes a signal. If this target is the master, it distributes edgeon the specified FPGA I/O line on the next falling edge of the CPTR (when edge is high). If this target is not the master, it ignores edge. All targets, master or otherwise, also read the FPGA I/O line. The synchronized edge output goes high on the next CPTR edge after the edge is read from the FPGA I/O line.
The input edge should be a pulse. This is enforced by the node. There is a rising edge detector in the edge input. Additionally, after an edge is seen, another edge is not recognized until after the edge distribution completes. This means that the minimum time between edges for synchronization is one to two CPTR periods, depending on when the edge is seen within the CPTR period. Two physical connection topologies, bus and star, are supported. In the bus topology, all targets are connected to a common bus, usually the AUX I/O. In the star topology, the master is connected to all the slaves, usually with PPS TRIG, and also back to itself.