The input being synchronized. Because the first block this input encounters is a rising edge detector, the input signal edge is treated as a pulse.
A Boolean that specifies whether to synchronize the input edge or not.
The sync.fpga io may be floating until a target is specified as the master. enable should be FALSE until after the host Synchronization node executes to prevent erroneous outputs on synchronized edge.
The FPGA I/O lines to send and receive the synchronization signals on.
Measurement clock used by the measurement logic. This clock must run at twice the rate of the FPGA Clock, which is the clock that drives the clock-driven loop (CDL) that this node is in. This clock must also derive from the FPGA Clock so that it has a fixed phase relationship. This clock is commonly Data Clock x2.
The "start" signal used by the measurement logic. When you use the FPGA Align node, the common reference must be the same clock to which the FPGA clock of the target is locked.
The number of clock cycles of delay that were added by synchronizing the input edge. This value is zero if enableis FALSE. If enable is TRUE, this value is valid only on the master target.
The synchronized input edge if enable is TRUE.
The same instance that was passed in for sync.resources.
The synchronization instance. sync.resources is obtained from the Create node.
Installed By: LabVIEW Communications System Design Suite (introduced in 1.0)
Where This Node Can Run:
Desktop OS: none
FPGA: All devices
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