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Aligns the targets participating in synchronization before synchronizing a signal.


clock x2

Measurement clock used by the measurement logic. This clock must run at twice the rate of the FPGA Clock, which is the clock that drives the clock-driven loop (CDL) that this node is in. This clock must also derive from the FPGA Clock so that it has a fixed phase relationship. This clock is commonly Data Clock x2.


sync.resources 2

The same instance that was passed in for sync.resources.



The synchronization instance. sync.resources is obtained from the Create node.


common reference

The "start" signal used by the measurement logic. When you use FPGA Align, the common reference must be the same clock to which the FPGA Clock of the target is locked.