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    Clock-Driven Logic appears and behaves similarly to G Dataflow. However, the purpose of Clock-Driven Logic differs from the purpose of G, so Clock-Driven Logic includes elements that differ from G.

    The following table describes differences between Clock-Driven Logic and G Dataflow.

    Language Purposes Source Document Timing Node Color
    Clock-Driven Logic
    • Creating FPGA code that executes in one clock cycle at the clock rate you specify
    • Optimizing an FPGA application
    • Integrating FPGA IP into an FPGA application
    • Interacting with I/O and streaming data to and from the host
    • Clock-Driven Logic document (.gcdl file)
    • FPGA VI (place Clock-Driven Logic code inside a Clock-Driven Loop)

    Executes within one clock cycle at the rate of the clock you wire to the Clock-Driven Loop.

    G Dataflow
    • Creating code that processes and logs data on the host
    • Testing and simulating FPGA code during development
    • Creating a top-level FPGA VI that contains FPGA code
    • Integrating Multirate Dataflow into an FPGA application
    • Creating FPGA IP to implement G algorithms on an FPGA

    VI (.gvi file)

    Does not rely on a clock. You can control the execution rate of a loop using a Wait node or Wait Until Next Ms Multiple node.


    The color of a node serves only as a visual indication of the programming language you are using. Node colors do not affect node behavior.