The location to write data in memory on the FPGA target. The valid address range depends on the requested number of elements you specify when creating the input memory item. For example, if you specify a requested number of elements of 65536, the valid address range is 0–65535. If address exceeds the address range, the data will not be written to memory.
The data to write to the DRAM memory on the FPGA target.
Bytes of memory at the address to overwrite with data. Each bit of the binary representation of the integer corresponds to a byte of data at the address. If the bit is 1, the node overwrites the corresponding byte of memory. If the bit is 0, the corresponding byte retains the previous value. If the memory is only 256 bits wide, the node only processes the lower 32 bits of the byte enables.
A Boolean that specifies whether the next data point has arrived for processing. Wire the output valid output of an upstream node to this input to transfer data from the upstream node to this node.
The data point is valid and can be processed.
The data point is not valid.
Reference to a DRAM memory item.
ready for input
A Boolean that indicates whether this node is ready to accept new input data. Use a Feedback Node to wire this output to the ready for output input of an upstream node.
The node is ready to accept new input data.
The node is not ready to accept new input data.
If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the input valid terminal is TRUE during the following cycle.
Installed By: LabVIEW Communications System Design Suite (introduced in 1.0)
Where This Node Can Run:
Desktop OS: none
FPGA: All devices
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