Writes an element to an FPGA FIFO.
The data element you would like to write to the FIFO. This data may be lost if the FIFO is full. Use ready for input or full threshold met? to determine if data may safely be written to the FIFO.
A Boolean that determines whether the next data point has arrived for processing. This input is generally wired to the output valid output of an upstream node.
ready for input
A Boolean that returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the ready for output input of an upstream node.