A Boolean that specifies whether downstream nodes are ready for this node to return a new value. Use a Feedback Node to wire the ready for input output of a downstream node to this input of the current node.
The downstream node is ready for the next data point.
The downstream node is not ready for the next data point.
If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
Reference to a DRAM memory item.
The data this node retrieves from the DRAM memory on the FPGA target.
A Boolean that indicates whether this node has computed a result that downstream nodes can use. Wire this output to the input valid input of a downstream node to transfer data from the node to the downstream node.
The node has computed a result that downstream nodes can use.
The node has not computed a result that downstream nodes can use.
Installed By: LabVIEW Communications System Design Suite (introduced in 1.0)