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Implements many different Reed-Solomon coding standards.The core is fully synchronous, using a single clock, and supports continuous input data with no gap between code blocks. The core is parameterizable, allowing you to control the symbol size, the code block length, the number of errors corrected, and the control signal behavior. The Decoder supports both error and erasure decoding. It is delivered through the Xilinx CORE Generator system and integrates with the Xilinx design flow.

Need License: Yes

Interface: AXI4-Stream

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Installed By: LabVIEW Communications System Design Suite (introduced in 1.0)

Where This Node Can Run:

Desktop OS: none

FPGA: All devices