A Boolean that determines if the downstream node is ready to receive data. If ready for output is FALSE during a given cycle, output valid returns FALSE during that cycle, and no data is removed from the FIFO.
A reference to the FIFO that was read from.
The oldest data element in the FIFO. If the FIFO is empty, the returned element is undefined.
A Boolean that returns TRUE if this node has computed a result that downstream nodes can use.
Installed By: LabVIEW Communications System Design Suite (introduced in 1.0)
Where This Node Can Run:
Desktop OS: none
FPGA: All devices
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