Home > Support > NI Product Manuals > LabVIEW Communications System Design Suite 1.0 Manual

Generates fast, compact FIFO-style registers, delay lines, or time-skew buffers up to 256 bits wide and up to 1024 words deep using Select RAM in SRL16 or SRLC32 mode.You can create either fixed-length or variable-length shift registers, as well as specify output register capability with clock enable and synchronous controls.

Need License: No

connector_pane_image

Installed By: LabVIEW Communications System Design Suite (introduced in 1.0)

Where This Node Can Run:

Desktop OS: none

FPGA: All devices