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Generates configurable high-speed, compact filter implementations.The core is fully synchronous, using a single clock, and is highly parameterizable, allowing designers to control the filter type, data and coefficient widths, the number of filter taps, the number of channels, and so on. Multi-rate operation is supported. The core is delivered through the Xilinx CORE Generator System and integrates seamlessly with the Xilinx design flow.

Need License: No

Interface: AXI4-Stream

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Installed By: LabVIEW Communications System Design Suite (introduced in 1.0)

Where This Node Can Run:

Desktop OS: none

FPGA: All devices