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Implements Digital Up Converters (DUCs) and Digital Down Converters (DDCs) for a range of wireless interface standards based on system-level parameters.The core implementation is delivered through the Xilinx CORE Generator system and is designed to take advantage of the advanced features of Xilinx FPGA devices.

Need License: No

Interface: AXI4-Stream

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Installed By: LabVIEW Communications System Design Suite (introduced in 1.0)

Where This Node Can Run:

Desktop OS: none

FPGA: All devices