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Monitors AXI interfaces. When attached to an interface, this node actively checks for protocol violations and provides an indication of which violation occurred.

The checks are synthesizable versions of the System Verilog protocol assertions provided by ARM in the AMBA 4 AXI4, AXI4-Lite, and AXI4-Stream Protocol Assertion library.

Need License: No

Interface: AXI4-Stream

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Installed By: LabVIEW Communications System Design Suite (introduced in 1.0)

Where This Node Can Run:

Desktop OS: none

FPGA: All devices