Generates adder-, subtractor-, and adder/subtractor-based accumulators operating on signed or unsigned input.Inputs range from 1 to 256 bits wide. Outputs range from 1 to 258 bits.
Need License: No
Installed By: LabVIEW Communications System Design Suite (introduced in 1.0)
Where This Node Can Run:
Desktop OS: none
FPGA: All devices