Home > Support > NI Product Manuals > LabVIEW Communications System Design Suite 1.0 Manual

Digitally controls the I and Q signal levels. This node must be used inside a Clock-Driven Loop. This node provides the following functionality: data out.I <= data in.I * gain I data out.Q <= data in.Q * gain Q Where "*" represents scalar multiplication.

Samples Per Cycle (SPC) Use the Function Gallery to change the number of parallel samples used on the 'data in' and 'data out' terminals. For multiple samples per cycle, 'data in' and 'data out' become fixed size arrays of SPC elements. The first element, data[0], is the oldest sample in the array.

Overflows Gain values greater than 1.0 (or less than or equal to -1.0) may cause overflows (signal clipping) to occur. Overflows on 'data in.overflow' are pipelined along with the data path, combined with overflows that occur inside this node, and output on 'data out.overflow'.

Reset Toggling the 'reset' input high resets the registers in the 'output valid' path, allowing for deterministic startup behavior. The registers in the 'data out' path are not reset, however 'output valid' is held low while 'reset' is asserted and does not assert after reset until the registers in the 'data out' path have been flushed. While reset is asserted 'ready for input' is held low and 'input valid' is ignored.

Pipeline Delay 5 clock cycles

Approximate resource usage in a Xilinx Virtex-5 or Virtex-6 Slice flip-flops: 2550 Slice LUTs: 2550 Block RAMs (18kb): 0 DSP48E(1)s: 32

Approximate maximum clock rate in a Xilinx Virtex-5 or Virtex-6 (-1) 160 MHz


Installed By: LabVIEW Communications System Design Suite (introduced in 1.0)

Where This Node Can Run:

Desktop OS: none

FPGA: All devices