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Synchronously realizes a signal.

If this target is the master, it distributes edge on the specified FPGA I/O line on the next falling edge of the CPTR when edge is high. If this target is not the master, it ignores edge. All targets also read the FPGA I/O line. The synchronized edge output goes high on the next CPTR edge after the edge is read from the FPGA I/O line.

The input, edge, should be a pulse. This is enforced by the node. The edge input contains a rising edge detector. After an edge is detected, another edge is not recognized until after the edge distribution has completed. Therefore, the minimum time between edges for synchronization is one to two CPTR periods, depending on when the edge is detected within the CPTR period.

Input Parameters

  • sync.resources identifies the Synchronization instance. sync.resources is obtained from ni579x Create.
  • sync.cptr.FPGA I/O is the FPGA I/O line that distributes/reads the edge for synchronization. This signal is commonly a PXI trigger line.

    For large NI chassis, ensure the same PXI trigger line is routed to all bus segments that have targets participating in synchronization.

  • enable specifies whether to synchronize the input edge.

    If the sync.cptr.FPGA I/O is a PXI trigger line, it will be floating until a target is specified as the master. The enable parameter should be FALSE until after the host Synchronization node executes in order to prevent erroneous outputs on synchronized edge.

  • edge is the input being synchronized. The first block this input encounters is a rising edge detector, so the input signal, edge, is treated as a pulse.

Output Parameters

  • sync.resources returns the same instance that was passed in for sync.resources.
  • synchronization delay returns the number of clock cycles of delay that were added by synchronizing the input edge. This value is zero if enable is FALSE. If enable is true, this value is only valid on the master target.
  • synchronized edge returns the synchronized input edge if enable is set to TRUE.

    If enable is true, it's possible that synchronized edge will be spuriously true before the host Synchronization nodes are run. NI recommends that you set enable to FALSE until after the host Synchronization node executes.


Installed By: LabVIEW Communications System Design Suite (introduced in 1.0)

Where This Node Can Run:

Desktop OS: none

FPGA: All devices