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    Number of general-purpose channels 136, configurable as 136 single-ended, 68 differential, or a combination of both [1]
    Channels per bank
    Bank 0/Bank 1 48
    Bank 2 40
    Compatibility Configured through the FPGA and based on the attached adapter module; 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V I/O standards (refer to xilinx.com).
    Protection Refer to xilinx.com.
    Current Refer to xilinx.com.
    Maximum I/O data rates
    Single-ended 400 Mb/s
    Differential 1 Gb/s for LVDS
    Multi-region clock inputs 6
    Single-region clock inputs 5
    Connection resources PXI triggers, PXI_CLK10, PXI star trigger, PXIe_DStarA, PXIe_DStarB, PXIe_DStarC, and PXIe_Sync100
    • 1 The 136 channels span across three FPGA banks.