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Configures the specified output power.

This node performs the following actions to configure the specified output power:

  • Configures the Tx front end attenuators and filters
  • Returns the I/Q impairment correction data, which you can use to correct I/Q impairments
  • Returns the residual digital gain that you can apply to the signal to achieve the specified output power
  • Sets the RF filter to the specified frequency

Input Parameters

  • Register Bus—The Register Bus object created by the ni579x Open node and used as the session handle for the NI-579x Configuration nodes.
  • scope—Specifies which channel to configure.
  • output power [dBm]—Specifies the power, in dBm, at the output terminal of the device that corresponds to the full-scale range of the DAC binary data.
  • correct IQ imbalance?—Specifies whether to calculate the I/Q impairment correction values. Set this parameter to FALSE if you are not using the I/Q impairment correction DSP blocks in the FPGA.
  • characterization data—A set of data that describes the characteristics of this device that allow the node to calculate the proper attenuation and I/Q imbalance correction settings for the specified frequency. This data is stored in the EEPROM and can be retrieved using the ni579x Load Characterization Data (Single Channel) node. For the NI 5791, the Tx data is index 1 in the array of characterization data returned by the ni579x Load Characterization Data (Single Channel) node.

Output Parameters

  • Register Bus (out)—The Register Bus object created by the ni579x Open node and used as the session handle for the NI-579x Configuration nodes.
  • coerced output power [dBm]—The actual output power the device was configured to, not including any additional digital gain applied by the DSP block in the FPGA.
  • digital gain—Applies residual digital gain values to the DSP Gain block in the FPGA.
  • IQ impairment correction—The values to apply to the I/Q Impairment Correction DSP block in the FPGA, in order to correct gain and phase imbalances in the mixer.
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Installed By: LabVIEW Communications System Design Suite (introduced in 1.0)

Where This Node Can Run:

Desktop OS: Windows

FPGA: Not supported