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Version:
    ADC (TI ADS4246) [1]
    Resolution 14 bits
    Data rate 130 MS/s [2]
    Samples per cycle 1
    DAC (TI DAC3482)
    Resolution 16 bits
    Data rate 130 MS/s (automatically interpolated to 520 MS/s)
    Samples per cycle 1
    • 1 ADCs and DACs are dual-channel components with each channel assigned to I and Q, respectively.
    • 2 Use the Fractional Interpolation and Decimation DSP blocks implemented in the LabVIEW FPGA target to decimate and interpolate the data.