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    The NI PXIe-1082 chassis supplies PXI_CLK10, PXIe_CLK100 and PXIe_SYNC100 to every peripheral slot with an independent driver for each signal.

    An independent buffer (having a source impedance matched to the backplane and a skew of less than 1 ns between slots) drives PXI_CLK10 to each peripheral slot. You can use this common reference clock signal to synchronize multiple modules in a measurement or control system.

    An independent buffer drives PXIe_CLK100 to each peripheral slot. These clocks are matched in skew to less than 100 ps. The differential pair must be terminated on the peripheral with LVPECL termination for the buffer to drive PXIe_CLK100 so that when there is no peripheral or a peripheral that does not connect to PXIe_CLK100, there is no clock being driven on the pair to that slot. Refer to the following figure for a termination example.

    An independent buffer drives PXIe_SYNC100 to each peripheral slot. The differential pair must be terminated on the peripheral with LVPECL termination for the buffer to drive PXIe_SYNC100 so that when there is no peripheral or a peripheral that does not connect to PXIe_SYNC100, there is no SYNC100 signal being driven on the pair to that slot. Refer to the following figure for a termination example.

    Figure 1. CLK100 Termination

    In summary, PXI_CLK10 is driven to every slot. PXIe_CLK100 and PXIe_SYNC100 are driven to every peripheral slot.

    PXI_CLK10, PXIe_CLK100 and PXIe_SYNC100 have the default timing relationship described in the following figure.

    Figure 2. System Reference Clock Default Behavior

    To synchronize the system to an external clock, you can drive PXI_CLK10 from an external source through the PXI_CLK10_IN pin on the System Timing Slot. Refer to Table B-5, XP4 Connector Pinout for the System Timing Slot, for the pinout. When a 10 MHz clock is detected on this pin, the backplane automatically phase-locks the PXI_CLK10, PXIe_CLK100, and PXIe_SYNC100 signals to this external clock and distributes these signals to the slots. Refer to the Specifications section for the specification information for an external clock provided on the PXI_CLK10_IN pin of the system timing slot.

    You also can drive a 10 MHz clock on the 10 MHz REF IN connector on the rear of the chassis. When a 10 MHz clock is detected on this connector, the backplane automatically phase-locks the PXI_CLK10, PXIe_CLK100, and PXIe_SYNC100 signals to this external clock and distributes these signals to the slots. Refer to the Specifications section for the specification information for an external clock provided on the 10 MHz REF IN connector on the rear panel of the chassis.

    If the 10 MHz clock is present on both the PXI_CLK10_IN pin of the System Timing Slot and the 10 MHz REF IN connector on the rear of the chassis, the signal on the System Timing Slot is selected. Refer to the following table which explains how the 10 MHz clocks are selected by the backplane.

    Table 1. Backplane External Clock Input Configuration
    System Timing Slot PXI_CLK10_IN Rear Chassis Panel 10 MHz REF IN Backplane PXI_CLK10, PXIe_CLK100 and PXIe_SYNC100
    No clock present No clock present Backplane generates its own clocks
    No clock present 10 MHz clock present PXI_CLK10, PXIe_CLK100 and PXIe_SYNC100 all phase-locked to Rear Chassis Panel—10 MHz REF IN
    10 MHz clock present No clock present PXI_CLK10, PXIe_CLK100 and PXIe_SYNC100 all phase-locked to System Timing Slot— PXI_CLK10_IN
    10 MHz clock present 10 MHz clock present PXI_CLK10, PXIe_CLK100 and PXIe_SYNC100 all phase-locked to System Timing Slot— PXI_CLK10__IN
    A copy of the backplane’s PXI_CLK10 is exported to the 10 MHz REF OUT connector on the rear of the chassis. This lock is driven by an independent buffer.