PXIe_SYNC100 is by default a 10 ns pulse synchronous to PXI_CLK10. The frequency of PXIe_SYNC100 is 10/n MHz, where n is a positive integer. The default for n is 1, giving PXIe_SYNC100 a 100 ns period. However, the backplane allows n to be programmed to other integers. For example, setting n = 3 gives a PXIe_SYNC100 with a 300 ns period while still maintaining its phase relationship to PXI_CLK10. The value for n can be any positive integer from 1 to 255.
The system timing slot has a control pin for PXIe_SYNC100 called PXIe_SYNC_CTRL for use when n > 1.
By default, a high-level detected by the backplane on the PXIe_SYNC_CTRL pin causes a synchronous restart for the PXIe_SYNC100 signal. On the next PXI_CLK10 edge the PXIe_SYNC100 signal restarts. This allows several chassis to have their PXIe_SYNC100 in phase with each other. Refer to the following figure for timing details with this method.