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NI-5772 Synchronized Reference Clock CLIP I/O Reference

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    Last Modified: April 26, 2017
    CLIP Signal Name Data Type Control/Indicator Description
    AI 0 Data N-3 I16 Indicator Reads analog data from the adapter module.

    Each sample is a left-justified I16 data type.

    If AI 0 is configured for TIS mode, these signals return time-interleaved samples for AI 0.

    AI 0 Data N-2
    AI 0 Data N-1
    AI 0 Data N
    AI 1 Data N-3 I16 Indicator Reads analog data from the adapter module.

    Each sample is a left-justified I16 data type.

    If AI 1 is configured for TIS mode, these signals return time-interleaved samples for AI 1.

    AI 1 Data N-2
    AI 1 Data N-1
    AI 1 Data N
    AI 0 Over Range N-3 Boolean Indicator Indicates that the input signal is beyond the full-scale range.

    This signal is synchronous to the analog input data.

    • TRUE: The input signal on either the AI 0 or AI 1 front panel connectors is beyond the full-scale range.
    • FALSE: The input signal is not over range.
    AI 0 Over Range N-2
    AI 0 Over Range N-1
    AI 0 Over Range N
    AI 1 Over Range N-3 Boolean Indicator Indicates that the input signal is beyond the full-scale range.

    This signal is synchronous to the analog input data.

    • TRUE: The input signal on either the AI 0 or AI 1 front panel connectors is beyond the full-scale range.
    • FALSE: The input signal is not over range.
    AI 1 Over Range N-2
    AI 1 Over Range N-1
    AI 1 Over Range N
    Initialization Done Bool Indicator Indicates whether the device is ready to use.
    • TRUE: The device is ready to use after the CLIP runs an initial default setup. The sampled data is valid.
    • FALSE: The device is not ready.
    PLL Locked Boolean Indicator

    Indicates whether the phase-locked loop (PLL) is locked.

    This signal is valid only when using a Reference Clock, either through the CLK IN connector or through the Sync Clock or IoModSyncClock.

    • TRUE: The PLL is locked.
    • FALSE: The PLL is not locked or you are not using a Reference Clock.
    User Command U8 Control Configures the clocking, ADC, sampling, and other settings for your device.

    Use this signal in conjunction with the User Data 0 and User Data 1 signals to select values for these settings. Apply these settings by selecting the User Command Commit signal.

    Refer to the User Command Reference for information about values for this signal.

    User Command Commit Boolean Control Applies the settings configured with the User Command signal.
    User Command Idle Boolean Indicator Indicates whether the device is prepared to accept more commands from the User Command signal.
    • TRUE: The device is prepared to accept more commands from the User Command signal.
    • FALSE: The device is not prepared to accept more commands.
    User Data 0 U8 Control Specifies configuration for the command in the User Command signal.

    Use the User Command, User Data 0, and User Data 1 signals to configure your device.

    Refer to the User Command Reference for information about values for this signal.

    User Data 1 U8 Control Specifies configuration for the command in the User Command signal.

    Use the User Command, User Data 0, and User Data 1 signals to configure your device.

    Refer to the User Command Reference for information about values for this signal.

    User Command Status U8 Indicator Indicates whether the previous command completed successfully.
    • 0 = Successful
    • 1 = The command does not exist
    • 2 = Option does not exist
    • 3 = The SPI device is undefined
    User Return U16 Indicator Returns data configured by the User Command signal.
    User Error U8 Indicator Indicates that an error occurred and you must reinitialize the device.
    • 0 = No error
    • Nonzero = Error
    Asynchronous Trigger Input[1] Boolean Indicator Indicates whether the FPGA received an unclocked trigger signal from the TRIG front panel connector.
    • TRUE: The FPGA has received a trigger signal.
    • FALSE: The FPGA has not received a trigger signal.
    Synchronous Trigger Input N-3[1] U8 Indicator Returns the time the FPGA received a trigger signal from the TRIG front panel connector in relation to the samples taken.

    Although synchronous to the ADC data, the latency through the trigger is different than the ADC. The buffers in the trigger path limit the bandwidth of like signals to less than 320 MB/s.

    Synchronous Trigger Input N-2[1]
    Synchronous Trigger Input N-1[1]
    Synchronous Trigger Input N[1]
    Trigger Output Boolean Control Writes a trigger signal through the TRIG front panel connector.
    • TRUE: Write a trigger signal.
    • FALSE: Do not write a trigger signal.
    Trigger WE Boolean Control Configures the TRIG front panel connector for either reading or writing a trigger signal.
    • TRUE: Enable the Trigger Output signal.
    • FALSE: Enable the Asynchronous Trigger Input and the Synchronous Trigger Input signals.
    DIO Port 0 Rd Data[2] U8 Indicator Reads data through the AUX I/O connector on the DIO port channels <0..3>.

    For example, for DIO Port 0, bit 0 corresponds with DIO Port (0), bit 1 corresponds with DIO Port (1), and so on. The upper four bits of the U8 are unused.

    DIO Port 0 Wr Data[2] U8 Control Writes data through the AUX I/O connector on the DIO port channels <0..3>.

    For example, for DIO Port 0, bit 0 corresponds with DIO Port (0), bit 1 corresponds with DIO Port (1), and so on. The upper four bits of the U8 are unused.

    DIO Port 0 WE Request[2] Boolean Configures the DIO port channels <0..3> on the AUX I/O connector for reading or writing.
    • TRUE: Writing enabled.
    • FALSE: Reading enabled (output tristated).
    DIO Port 0 WE Actual[2]
    DIO Port 1 Rd Data[2] U8 Indicator Reads data through the AUX I/O connector on the DIO port channels <0..3>.

    For example, for DIO Port 0, bit 0 corresponds with DIO Port (0), bit 1 corresponds with DIO Port (1), and so on. The upper four bits of the U8 are unused.

    DIO Port 1 Wr Data[2] U8 Control Writes data through the AUX I/O connector on the DIO port channels <0..3>.

    For example, for DIO Port 0, bit 0 corresponds with DIO Port (0), bit 1 corresponds with DIO Port (1), and so on. The upper four bits of the U8 are unused.

    DIO Port 1 WE Request[2] Boolean Control Configures the DIO port channels <0..3> on the AUX I/O connector for reading or writing.
    • TRUE: Writing enabled.
    • FALSE: Reading enabled (output tristated).
    DIO Port 1 WE Actual[2]
    PFI 0 Rd Data[2] Boolean Indicator Reads data through the AUX I/O connector on the PFI line.
    PFI 0 Wr Data[2] Boolean Control Writes data through the AUX I/O connector on the PFI line.
    PFI 0 WE[2] Boolean Control Configures the PFI line on the AUX I/O connector for reading or writing.
    • TRUE: Writing enabled.
    • FALSE: Reading enabled (output tristated).
    PFI 1 Rd Data[2] Boolean Indicator Reads data through the AUX I/O connector on the PFI line.
    PFI 1 Wr Data[2] Boolean Control Writes data through the AUX I/O connector on the PFI line.
    PFI 1 WE[2] Boolean Control Configures the PFI line on the AUX I/O connector for reading or writing.
    • TRUE: Writing enabled.
    • FALSE: Reading enabled (output tristated).
    PFI 2 Rd Data[2] Boolean Indicator Reads data through the AUX I/O connector on the PFI line.
    PFI 2 Wr Data[2] Boolean Control Writes data through the AUX I/O connector on the PFI line.
    PFI 2 WE[2] Boolean Control Configures the PFI line on the AUX I/O connector for reading or writing.
    • TRUE: Writing enabled.
    • FALSE: Reading enabled (output tristated).
    PFI 3 Rd Data[2] Boolean Indicator Reads data through the AUX I/O connector on the PFI line.
    PFI 3 Wr Data[2] Boolean Control Writes data through the AUX I/O connector on the PFI line.
    PFI 3 WE[2] Boolean Control Configures the PFI line on the AUX I/O connector for reading or writing.
    • TRUE: Writing enabled.
    • FALSE: Reading enabled (output tristated).
    SPI Idle Boolean Indicator Indicates when the SPI interface to either the clock circuit or ADC is being accessed.

    To use the SPI or Apply Settings signals, you must wait for this signal to be TRUE.

    SPI Device Select U8 Control Selects which SPI device to interact with.
    • 0 = ADC
    • 1 = PLL circuit
    SPI Address U16 Control Configures the SPI address to read and write data.

    Write data only to addresses supported by the selected device.

    SPI Write Data U32 Control Configures the SPI data to write to a selected device at a SPI address.
    SPI Read Data U8 Indicator Configures the SPI data to read from a selected device at a SPI address.
    SPI Read Boolean Control Executes the settings of the SPI Read Data signal when this signal is on a FALSE-to-TRUE transition.
    SPI Write Boolean Control Executes the settings of the SPI Write Data signal when this signal is on a FALSE-to-TRUE transition.
    Clock 40 MHz — Clock

    40 MHz base clock source.You can use this clock as a timebase for running your LabVIEW FPGA VI.

    The 40 MHz onboard clock is the default clock. This clock is generated from a PLL in the NI FlexRIO FPGA module. The PLL source is either PXIe_CLK100 or PXI_CLK10.

    Clock 200MHz — Clock 200 MHz base clock source.You can use this clock as a timebase for running code on your target FPGA. This clock is generated from a PLL in the NI FlexRIO FPGA module.
    Data Clock — Constant Clock FPGA clock used to sample input data.

    In real-time sampling mode, eight samples from each analog input channel are valid on every rising edge of this clock. In TIS mode, 16 samples from only one analog input channel are valid on each clock cycle. During TIS mode, the data in the CLIP signals appears to be coming from both AI 0 and AI 1, but one channel is returning time-interleaved samples for the other channel, which provides 16 total samples on one channel.

    Access only the analog input and over range signals in this clock domain.

    Refer to theUser Command Reference to learn how to configure one channel for TIS mode.

    Data Clock 2x — Reserved for future or internal use.
    • 1 Using synchronous triggers and asynchronous triggers simultaneously can cause CLIP compilation errors. Use only one trigger type in your node.
    • 2 All DIO and PFI signals can be accessed in any clock domain, but you still must comply with the physical clock capabilities of your device.

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