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Logical Shift (G Dataflow)

Version:
    Last Modified: December 12, 2016

    Shifts a specified input (x) the number of specified bits (y).

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    y

    An input of any numeric representation.

    If y is greater than 0, the node shifts x left y bits (from least significant to most significant bit) and inserts zeros in the low-order bits. If y is less than 0, the node shifts x right y bits in the positive direction (from most significant to least significant bit) and inserts zeros in the high-order bits.

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    x

    An input of any integer representation.

    If x is an 8-, 16-, 32-, or 64-bit integer and y is greater than 8, 16, or 32, or 64 or is less than -8, -16, -32, or -64, respectively, the output value is all zeros.

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    x << y

    The result of the shift and same numeric representation as x.

    Where This Node Can Run:

    Desktop OS: Windows

    FPGA: DAQExpress does not support FPGA devices


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