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Hardware-Timed Generations

    Last Modified: February 26, 2018

    With a hardware-timed generation, a digital hardware signal controls the rate of the generation. This signal can be generated internally on the controller or provided externally.

    Hardware-timed generations have several advantages over software-timed acquisitions:
    • The time between samples can be much shorter.

    • The timing between samples is deterministic.

    • Hardware-timed acquisitions can use hardware triggering.

    Hardware-Timed Single Point (HWTSP) Mode

    In HWTSP mode, samples are acquired or generated continuously using hardware timing and no buffer. You must use the sample clock or change detection timing types. No other timing types are supported.

    Use HWTSP mode if you need to know if a loop executes in a given amount of time, such as in a control application. Because there is no buffer, if you use HWTSP mode, ensure that reads or writes execute fast enough to keep up with hardware timing. If a read or write executes late, it returns a warning.

    Buffered Digital Output

    A buffer is a temporary storage in computer memory for generated samples. In a buffered generation, data is moved from a host buffer to the cRIO controller onboard FIFO before it is written to the C Series module(s).

    One property of buffered I/O operations is sample mode. The sample mode can be either finite or continuous:
    • Finite—Finite sample mode generation refers to the generation of a specific, predetermined number of data samples. After the specified number of samples is written out, the generation stops.

    • Continuous—Continuous generation refers to the generation of an unspecified number of samples. Instead of generating a set number of data samples and stopping, a continuous generation continues until you stop the operation. There are three different continuous generation modes that control how the data is written. These modes are regeneration, onboard regeneration, and non-regeneration:
      • In regeneration mode, you define a buffer in host memory. The data from the buffer is continually downloaded to the FIFO to be written out. New data can be written to the host buffer at any time without disrupting the output.
      • With onboard regeneration, the entire buffer is downloaded to the FIFO and regenerated from there. After the data is downloaded, new data cannot be written to the FIFO. To use onboard regeneration, the entire buffer must fit within the FIFO size. The advantage of using onboard regeneration is that it does not require communication with the main host memory once the operation is started, which prevents problems that may occur due to excessive bus traffic or operating system latency.

        Install parallel DO modules in slots 1 through 4 to maximize accessible FIFO size because using a module in slots 5 through 8 will reduce the accessible FIFO size.

      • With non-regeneration, old data is not repeated. New data must continually be written to the buffer. If the program does not write new data to the buffer at a fast enough rate to keep up with the generation, the buffer underflows and causes an error.

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