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Sample Clocked Buffered Two-Signal Separation Measurement

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    Last Modified: February 26, 2018

    A sample clocked buffered two-signal separation measurement is similar to single two-signal separation measurement, but buffered two-signal separation measurement takes measurements over multiple intervals correlated to a sample clock. The counter counts the number of rising (or falling) edges on the Source input occurring between an active edge of the Gate signal and an active edge of the Aux signal. The counter then stores the count in the FIFO on a sample clock edge. On the next active edge of the Gate signal, the counter begins another measurement. The sampled values will be transferred to host memory using a high-speed data stream.

    The figure below shows an example of a sample clocked buffered two-signal separation measurement.

    Figure 1. Sample Clocked Buffered Two-Signal Separation Measurement
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    Note  

    If an active edge on the Gate and an active edge on the Aux does not occur between sample clocks, an overrun error occurs.

    For information about connecting counter signals, refer to the Default Counter/Timer Routing section.


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