Table Of Contents

AI Convert Clock Signal Behavior For Analog Input Modules

    Last Modified: August 30, 2018

    Refer to the Scanned Modules, Simultaneous Sample-and-Hold Modules, Delta-Sigma Modules, and Slow Sample Rate Modules sections for information about the AI Convert Clock signal and C Series analog input modules.

    Scanned Modules

    Scanned C Series analog input modules contain a single A/D converter and a multiplexer to select between multiple input channels. When the module interface receives a Sample Clock pulse, it begins generating a Convert Clock for each scanned module in the current task. Each Convert Clock signals the acquisition of a single channel from that module. The Convert Clock rate depends on the module being used, the number of channels used on that module, and the system Sample Clock rate.

    The driver chooses the fastest conversion rate possible based on the speed of the A/D converter for each module and adds 10 µs of padding between each channel to allow for adequate settling time. This scheme enables the channels to approximate simultaneous sampling. If the AI Sample Clock rate is too fast to allow for 10 µs of padding, NI-DAQmx selects a conversion rate that spaces the AI Convert Clock pulses evenly throughout the sample. NI-DAQmx uses the same amount of padding for all the modules in the task. To explicitly specify the conversion rate, use the ActiveDevs and AI Convert Clock Rate properties using the DAQmx Timing property node or functions.

    Simultaneous Sample-and-Hold Modules

    Simultaneous sample-and-hold (SSH) C Series analog input modules contain multiple A/D converters or circuitry that allows all the input channels to be sampled at the same time. These modules sample their inputs on every Sample Clock pulse.

    Delta-Sigma Modules

    Delta-sigma C Series analog input modules function much like SSH modules, but use A/D converters that require a high-frequency oversample clock to produce accurate, synchronized data. Some delta-sigma modules in the cRIO controller automatically share a single oversample clock to synchronize data from all the modules that support an external oversample clock timebase when they all share the same task. (DSA modules are an example).

    The oversample clock is used as the AI Sample Clock Timebase. The cRIO controller supplies 10 MHz, 12.8 MHz, and 13.1072 MHz timebases from which software automatically selects based on the modules in the task. When delta-sigma modules with different oversample clock frequencies are used in an analog input task, the AI Sample Clock Timebase can use any of the available frequencies; by default, the fastest available is used. The sample rate of all modules in the task is an integer divisor of the frequency of the AI Sample Clock Timebase.

    When one or more delta-sigma modules are in an analog input task, the delta-sigma modules also provide the signal used as the AI Sample Clock. This signal is used to cause A/D conversion for other modules in the system, just as the AI Sample Clock does when a delta-sigma module is not being used.

    When delta-sigma modules are in an AI task, the controller automatically issues a synchronization pulse to each delta-sigma module so that their ADCs are reset at the same time. Because of the filtering used in delta-sigma A/D converters, these modules usually exhibit a fixed input delay relative to non-delta-sigma modules in the system. This input delay is specified in the C Series module documentation.

    When channels from delta-sigma C Series modules are included in a multi-chassis task, please ensure that the first channel in your channel list is from a delta-sigma module.


    DSA modules do not support HWTSP mode.

    Slow Sample Rate Modules

    Some C Series analog input modules are specifically designed for measuring signals that vary slowly, such as temperature. Because of their slow rate, it is not appropriate for these modules to constrain the AI Sample Clock to operate at or slower than their maximum rate. When using such a module in the cRIO controller mixed with a non-slow sample module in the same task, exceeding the maximum sampling rate of the slow sample module results in the most recently acquired sample being read multiple times. In this scenario, the first sample of a hardware-timed acquisition with a slow sampled C Series module is sampled when the task is committed.

    For more information about which C Series modules are compatible with the cRIO controller, go to and enter the Info Code rdcdaq.

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