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Minimum Discrepancy Timer

    Last Modified: September 6, 2017

    Dual input configurations introduce additional discrepancy. To compensate, the module FPGA sets a discrepancy timer based on the debounce filter time and test pulse width. Refer to the following table to calculate the minimum discrepancy timer values based on the configuration.

    Table 1. Calculating Minimum Discrepancy Timer Values
    Debounce Filter Time Dual Input Dual Input with Test Pulse
    0 μs < debounce filter time50 μs 100 μs
    50 μs < debounce filter time 2 × debounce filter time (2 × debounce filter time) + test pulse width

    You cannot set debounce filter time < 108 μs when using dual input with test pulse.

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