Dual input configurations introduce additional discrepancy. To compensate, the module FPGA sets a discrepancy timer based on the debounce filter time and test pulse width. Refer to the following table to calculate the minimum discrepancy timer values based on the configuration.
|Debounce Filter Time||Dual Input||Dual Input with Test Pulse|
|0 μs < debounce filter time ≤ 50 μs||100 μs||—|
|50 μs < debounce filter time||2 × debounce filter time||(2 × debounce filter time) + test pulse width|