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Detect Falling Edge (Clock-Driven Logic)

Version:
    Last Modified: August 4, 2018

    Detects a transition from True to False on the input signal. Use Detect Falling Edge inside a Clock-Driven Loop.

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    signal

    Signal on which to detect a transition.

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    edge detected

    Boolean value that indicates whether this node has detected the transition on the input signal.

    Where This Node Can Run:

    Desktop OS: none

    FPGA: Supported

    Web Server: Not supported in VIs that run in a web application


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