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D Latch (D Latch U8) (Clock-Driven Logic)

Version:
    Last Modified: August 4, 2018

    Latches the input data until it is cleared.

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    s

    Boolean value that specifies whether to copy the value of d to q.

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    d

    The data to be latched.

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    r

    Boolean value that specifies whether to reset q to 0.

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    q

    Copy of the value of d after it is cleared.

    Where This Node Can Run:

    Desktop OS: none

    FPGA: Supported

    Web Server: Not supported in VIs that run in a web application


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