To better understand the challenges connected with wideband streaming, one must first understand the technical specifications of the IF receiver. This paper focuses on the PXIe-5624R module. IF receivers are typically part of the vector signal analyzer that comprises the mixer, IF receiver, and signal sources for LO. The architecture of the example vector signal analyzer is described in the Introduction to the PXIe-5668R—High-Performance 26.5 GHz Wideband Signal Analyzer white paper.
IF is characterized by the frequency range from 5 MHz to 2 GHz and bandwidth of 800 MHz typical (see technical specs for details). After adding a band-limited noise (dither) signal, which helps reduce the quantization effects of the ADC and improve spectral performance, the ADC samples the signal at up to 2 GSa/s with 12-bit resolution. The onboard FPGA processes these samples and transfers the data to other devices (PXI Express controller, RAID) through the PCI Express Gen 2x8, which allows for data streaming with theoretical rates of up to 4 GB/s. In the wideband streaming case, the FPGA performs only one digital downconversion (DDC) for all incoming data, as opposed to several independent downconversions in the narrowband case as mentioned later in the document.
Figure 3. Block Diagram of the PXIe-5624R IF Digitizer
When talking about wideband streaming, one must consider not only the theoretical available bandwidth of the PCI Express bus but also its practical limitations (that is, control messages that travel over the same bus). The first and more simple implementation for sending data over the PCI Express bus would be to send 16-bit samples, one after another, even if data from the ADC is only 12 bit. However, this approach leads to theoretical limitations of 4 GB/s per PCI Express link available in the PXIe-5624R module (2 bytes/samples at 2 GS/s equals to 4 GB/s), which practically won’t allow for continuous streaming. However, there’s a clever solution: bit packing. Using bit packing, four 12-bit samples are packed into three 16-bit words. Consequently, this method reduces the data rate from 4 GB/s to 3 GB/s, enabling continuous data streaming.
Often there is a need for continuous streaming from several modules of the same type. These multichannel, synchronized RF systems enable certain applications such as direction finding. By analyzing the incoming signal’s phase difference between different channels, the system can determine the direction of the signal source.
In such case, the digitizers are locked to the same reference clock. By default, this is the 100 MHz PXI Express backplane clock. Therefore, the synchronization makes it possible to start the acquisition on multiple devices at the same time—more precisely, within a couple of 10 ps relative to each other. But, it is critical that the skew between the digitizers is the same from run to run as long as the temperature is the same, so the skew can be improved with calibration. No timing module or external cabling is required for the synchronization to work. The synchronization uses two trigger lines on the PXI Express backplane.
In burst mode, the data is streamed to the host only after the trigger signal occurs. The trigger signal can be connected directly to the IF digitizer board using the PFI0 connector, or it can be software-triggered. In burst mode, users can define logic of the FPGA in a way that a few parameters can be configured:
- Record length (Nx)
- Record period (Mx)
- Number of records per trigger
- Number of pretrigger samples
Figure 4. Example Burst Acquisition Scenario
Such a burst scenario can be implemented in a way that allows for variable record lengths and delays. Descriptions of scenarios can be defined on the host machine and later streamed down to the FPGA. The trigger signal, however, can produce samples with an uncertainty of around 8 ns, because the PFI0 signal being sampled at 125 MHz.
Figure 5. Trigger Uncertainty Resulting From PFI0 Being Sampled at 125 MHz